Power saving for reverse directory

Abstract

Embodiments include systems and methods for improving power consumption characteristics of reverse directories in microprocessors. Some embodiments operate in context of multiprocessor semiconductors having cache hierarchies in which multiple higher-level caches share lower-level caches. Lower-level cache is coupled with reverse directories associated with respective ones of the higher-level caches. Each reverse directory can be segregated into two reverse sub-directories, one reverse sub-directory for relatively high-frequency accesses (e.g., updating 'valid' and/or 'private' information), and the other reverse sub-directories for relatively low-frequency accesses updating “index” and “way” information). During a write mode operation, when the reverse directories are updated, the write operation is performed only on the sub-directories having the entries invoked by the update, such that write operations can frequently consume only a fraction (e.g., halt) of the power of a conventional reverse directory write operation.