The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Apr. 28, 2015
Applicant:

Qlogic Corporation, Aliso Viejo, CA (US);

Inventors:

Dharma R. Konda, Aliso Viejo, CA (US);

Rajendra R. Gandhi, Laguna Niguel, CA (US);

Ben K. Hui, Irvine, CA (US);

Bruce A. Klemin, Rocklin, CA (US);

Assignee:

QLOGIC Corporation, Aliso Viejo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 3/00 (2006.01); G06F 13/28 (2006.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 13/10 (2006.01); G06F 13/20 (2006.01);
U.S. Cl.
CPC ...
G06F 9/50 (2013.01); G06F 9/4881 (2013.01); G06F 9/5005 (2013.01); G06F 9/5011 (2013.01); G06F 9/5016 (2013.01); G06F 9/5022 (2013.01); G06F 9/5027 (2013.01); G06F 9/5033 (2013.01); G06F 9/5044 (2013.01); G06F 13/10 (2013.01); G06F 13/20 (2013.01); G06F 13/28 (2013.01);
Abstract

Methods and systems for routing control blocks is provided. One method includes receiving a control block from a computing device at an adapter having a plurality of hardware engines for processing control blocks, where the control blocks are to read data, write data, obtain status for an input/output request and perform a management task; evaluating the control block by the adapter to determine that the control block is a continuation control block for data transfer using more than one control block; is a direct route control block for a specific hardware engine; or is for a management task; routing the control block to a same hardware engine when the control block is a continuation control block; and routing the control block to a master hardware engine from among the plurality of hardware engines, when the control block is for the management task.


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