The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Jun. 29, 2015
Applicant:

Vijay Kumar Kodavalla, Bangalore, IN;

Inventor:

Vijay Kumar Kodavalla, Bangalore, IN;

Assignee:

Wipro Limited, Bangalore, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/32 (2006.01); H03L 7/18 (2006.01); H03L 7/10 (2006.01); H04B 15/02 (2006.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); H03L 7/10 (2013.01); H03L 7/18 (2013.01); H04B 15/02 (2013.01); H04B 2215/065 (2013.01);
Abstract

This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device. In one embodiment, a method is provided for dynamically adjusting a low power clock frequency of a host device. The method comprises dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational, computing a low power clock frequency range of the host device based on the initial frequency of the low power clock, assessing the low power link in the low power clock frequency range, and adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.


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