The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
May. 19, 2014
Applicant:
Mentor Graphics Corporation, Wilsonville, OR (US);
Inventors:
Shi-Yu Huang, Taoyuan County, TW;
Kun-Han Tsai, Lake Oswego, OR (US);
Wu-Tung Cheng, Lake Oswego, OR (US);
Jeo-Yen Lee, Taipei, TW;
Assignee:
Mentor Graphics, A Siemens Business, Wilsonville, OR (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31717 (2013.01); G01R 31/31855 (2013.01);
Abstract
Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.