The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Aug. 18, 2014
Applicant:

Duke University, Durham, NC (US);

Inventors:

Sergej Deutsch, Austin, TX (US);

Krishnendu Chakrabarty, Chapel Hill, NC (US);

Assignee:

Duke University, Durham, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G06F 11/34 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31703 (2013.01); G01R 31/31705 (2013.01); G06F 11/348 (2013.01); G06F 11/3636 (2013.01);
Abstract

A post-fabrication debug and on-line error checking framework for 2D- and 3D-ICs with integrated memories is described. A design-for-debug (DfD) architecture can include, for an IC with on-chip memory, a debug module connected to a functional bus of the IC. The debug module receives trace data for an interval, generates compact signatures based on the received data, and compares these signatures to expected signatures. Intervals containing erroneous trace data can be identified by the debug module and stored in on-chip memory. A single iteration of signal tracing for debug testing between automated test equipment and the IC is possible.


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