The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Jul. 28, 2016
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Peng Ren, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); B81C 1/00 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 21/67 (2006.01); H01L 21/687 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00801 (2013.01); H01L 21/6715 (2013.01); H01L 21/67063 (2013.01); H01L 21/687 (2013.01); H01L 21/76861 (2013.01); H01L 21/76873 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/02 (2013.01); H01L 24/13 (2013.01); B81C 2201/0154 (2013.01); B81C 2201/05 (2013.01); B81C 2203/0778 (2013.01); H01L 2224/02317 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/13024 (2013.01);
Abstract

A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.


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