The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2017
Filed:
Jul. 10, 2014
Applicant:
Sony Corporation, Tokyo, JP;
Inventors:
Toshiyuki Inaoka, Ishikawa, JP;
Atsuhiro Uratsuji, Ishikawa, JP;
Assignee:
Other;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0271 (2013.01); H05K 3/465 (2013.01); H05K 1/181 (2013.01); H05K 3/0032 (2013.01); H05K 2201/10121 (2013.01);
Abstract
A multilayer wiring substrate, a method of producing and a semiconductor product includes: a trench produced at one surface of an insulation layer, the trench having a depth shallower than a thickness of the insulation layer; and a copper plating applied to the trench.
Inaoka, Toshiyuki. (2017). Multilayer wiring substrate, method of producing the same, and semiconductor product (U.S. Patent No. 9717142). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9717142
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile