The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2017

Filed:

May. 12, 2015
Applicant:

Teledyne Scientific & Imaging, Llc, Thousand Oaks, CA (US);

Inventor:

Mihail Milkov, Moorpark, CA (US);

Assignee:

TELEDYNE SCIENTIFIC & IMAGING, LLC, Thousand Oaks, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03K 4/08 (2006.01); H03M 1/56 (2006.01); H03M 1/08 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1245 (2013.01); H03K 4/08 (2013.01); H03M 1/08 (2013.01); H03M 1/56 (2013.01);
Abstract

Comparator circuits suitable for use in a column-parallel single-slope ADC comprise a comparator, an input voltage sampling switch connected between an input voltage Vand a first node, and a sampling capacitor connected between the first and second nodes and which stores a voltage which varies with Vwhen the sampling switch is closed. A first reset switch is connected between the second node and a reset voltage, an isolation buffer is coupled between the second node and a comparator input, and a voltage ramp switch applies a voltage ramp Vto the first node when closed. The comparator output toggles when Vexceeds V, with the isolation buffer maintaining a nearly constant capacitive load on V. A 'ramp disconnect' feature can be used to increase the circuit's input range, and a dummy capacitor can be employed to maintain a constant capacitance on V.


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