The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2017

Filed:

Jun. 15, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lior Binyamini, Holon, IL;

Stefan Payer, Stuttgart, DE;

Wolfgang Penth, Holzgerlingen, DE;

Ido Rozenberg, Rishon le-Zion, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/44 (2006.01); G11C 11/419 (2006.01); G11C 29/12 (2006.01); G06F 11/10 (2006.01); G11C 29/54 (2006.01);
U.S. Cl.
CPC ...
G11C 29/44 (2013.01); G06F 11/106 (2013.01); G11C 11/419 (2013.01); G11C 29/12 (2013.01); G11C 29/54 (2013.01);
Abstract

A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0≦i≦n−1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.


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