The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2017

Filed:

May. 23, 2016
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Jun Sumino, Boise, ID (US);

Makoto Kitagawa, Folsom, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/0002 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0097 (2013.01); G11C 13/0061 (2013.01); G11C 2013/0085 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.


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