The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2017

Filed:

Jul. 05, 2016
Applicant:

Xitore, Inc., Mission Viejo, CA (US);

Inventor:

Mike Hossein Amidi, Lake Forest, CA (US);

Assignee:

XITORE, INC., Mission Viejo, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/18 (2006.01); G06F 3/06 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0608 (2013.01); G06F 3/0631 (2013.01); G06F 3/0688 (2013.01); G06F 12/00 (2013.01);
Abstract

A fast and lean way of performing logical-to-physical address translation is presented. A logical address is divided into a most significant bits portion and a least significant bits portion. Instead of using the entire logical address to locate an entry in an address translation table, only the most significant bits portion of the logical address is used, which substantially reduces the size of the address translation table. The entry includes a most significant bits portion of a physical volatile memory address and a most significant bits portion of a physical non-volatile memory address. The actual physical volatile memory address and the actual physical non-volatile memory address can be derived by combining the most significant bits portions of the addresses stored in the address translation table entry with the least significant bits portion of the logical address.


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