The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2017

Filed:

Jun. 08, 2016
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Takahiro Ochiai, Chiba, JP;

Mitsuru Goto, Chiba, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); G02F 1/1333 (2006.01); G02F 1/13 (2006.01); H01L 23/00 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13452 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/13458 (2013.01); G02F 1/133345 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 27/124 (2013.01); G02F 2001/136254 (2013.01);
Abstract

A display device includes a transparent substrate having a display region with a plurality of scanning signal lines and video signal lines intersecting thereon, a first terminal formed outside the display region connecting to a first terminal wiring and a second terminal wiring connected to a semiconductor chip, and an inverted staggered thin film transistor. The first terminal includes a first portion, a second portion on the first portion, a third portion having an exposed planar terminal plate on the second portion, a plurality of first vias between the first portion and the second portion, and a plurality of second vias between the second portion and the third portion. The first portion is connected to the first and second terminal wirings, and each of the plurality of first vias is not overlapped with each of the plurality of second vias in plan view.


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