The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Nov. 21, 2012
Applicant:

Versitech Limited, Hong Kong, CN;

Inventors:

Ron Shu Yuen Hui, Hong Kong, CN;

Sinan Li, Heilongjiang, CN;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 3/16 (2006.01); G05F 3/26 (2006.01); H05B 33/08 (2006.01);
U.S. Cl.
CPC ...
H05B 33/083 (2013.01); G05F 3/16 (2013.01); H05B 33/089 (2013.01); H05B 33/0827 (2013.01); G05F 3/26 (2013.01);
Abstract

Provided is a current mirror circuit () for balancing respective currents in a plurality of parallel circuit branches () in a target circuit (), the current mirror circuit () including: a plurality of balancing transistors (), each having a connector (), an emitter (), and a base (), the collector () and emitter () of each balancing transistor () connected in series with a respective circuit branch (); a selection circuit () that connects the circuit branch () having the smallest current amongst the circuit branches () to the bases () of each balancing transistor; and an isolation circuit () that isolates circuit branches () having an open circuit fault from the rest of the target circuit (). An associated method of balancing respective currents in a plurality of parallel circuit branches () in a target circuit () is also provided.


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