The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Aug. 08, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Takeshi Takagi, Yokkaichi, JP;

Takeshi Yamaguchi, Yokkaichi, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/146 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 45/08 (2013.01); H01L 45/145 (2013.01); H01L 45/16 (2013.01); H01L 45/1633 (2013.01);
Abstract

According to one embodiment, a plurality of first wirings are disposed in a first direction and a second direction which intersect with each other, and extended in a third direction. A second wiring stack is configured to include second wirings and interlayer insulating films which are extended and alternately stacked in the second direction. A memory cell includes, in the first direction, a first variable resistive layer which is disposed on a side near the first wiring and a second variable resistive layer which is disposed on a side near the second wiring. The second variable resistive layer is disposed between the interlayer insulating films in the third direction, and made of a material which is obtained by oxidizing the second wiring.


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