The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Oct. 13, 2015
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventors:

Takahiro Tamura, Matsumoto, JP;

Yasuhiko Onishi, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/263 (2006.01); H01L 29/868 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 21/263 (2013.01); H01L 29/06 (2013.01); H01L 29/0634 (2013.01); H01L 29/0688 (2013.01); H01L 29/0878 (2013.01); H01L 29/0882 (2013.01); H01L 29/1095 (2013.01); H01L 29/66121 (2013.01); H01L 29/66333 (2013.01); H01L 29/66712 (2013.01); H01L 29/7395 (2013.01); H01L 29/7803 (2013.01); H01L 29/868 (2013.01);
Abstract

A super junction MOSFET includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an nregion with a lower impurity concentration than the n-type drift region. With this structure, it is possible to provide a super junction MOSFET which prevents a sharp rise in hard recovery waveform during a reverse recovery operation.


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