The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Nov. 25, 2015
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Sang Eun Lee, Chuncheon-si, KR;

Eun Ko, Seoul, KR;

Yong Jae Park, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/73 (2013.01); H01L 23/3675 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/96 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01); H01L 24/32 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83005 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. The semiconductor package may also include a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips. The semiconductor package may also include via patterns formed in the first encapsulation member. The semiconductor package may also include second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips. Second bonding pads electrically connected to the via patterns are arranged over bottom surfaces of the second semiconductor chips. The semiconductor package may also include a second encapsulation member formed over the top surfaces of the first semiconductor chips and the first encapsulation member to surround at least side surfaces of the second semiconductor chips.


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