Processor with ray test instructions performed by special purpose units

Abstract

A processor supports special-purpose instructions relating to testing rays for intersection with geometry and acceleration structure elements. The processor can be a full-featured processor; the special-purpose instructions can be differentiated from other supported instructions. The processor can have an instruction generator coupled with an instruction decoder, a data cache, a fetch unit, and a set of test cells for performing computations indicated by special-purpose instructions. Separate test cells can test rays with scene geometry and with acceleration structure elements; different instructions can be provided for each type of testing. The data cache is coupled to the test cells; the instruction decoder also provides input to the test cells while the test cells are coupled to a write back unit that is coupled to the data cache and to the instruction generator. In an example, the instruction decoder supplies ray references from an instruction as functional addresses to the data cache.