The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Jul. 29, 2016
Applicant:

Movellus Circuits, Inc., Ann Arbor, MI (US);

Inventors:

Jeffrey Alan Fredenburg, Ann Arbor, MI (US);

Muhammad Faisal, Ann Arbor, MI (US);

David Michael Moore, Ann Arbor, MI (US);

Assignee:

Movellus Circuits, Inc., Ann Arbor, MI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/099 (2006.01); H03L 7/081 (2006.01); H03B 5/12 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0995 (2013.01); H03B 5/124 (2013.01); H03B 5/1228 (2013.01); H03L 7/0814 (2013.01);
Abstract

A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and delay generator is configured as the delay line circuit.


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