The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Sep. 23, 2016
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Ja Yol Lee, Nonsan-si, KR;

Min Jae Lee, Gwangju, KR;

Cheon Soo Kim, Daejeon, KR;

Min Uk Heo, Gwangju, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); H03L 7/18 (2006.01); H03L 7/091 (2006.01); H03L 7/093 (2006.01); H03L 7/085 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0991 (2013.01); H03L 7/085 (2013.01); H03L 7/091 (2013.01); H03L 7/093 (2013.01); H03L 7/18 (2013.01);
Abstract

Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.


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