Self-calibrating fractional-n phase lock loop and method thereof

Abstract

A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise and an output of the timing detection circuit.