The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

May. 26, 2016
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Naofumi Hayashi, Osaka, JP;

Mitsuaki Morigami, Osaka, JP;

Masato Shigematsu, Osaka, JP;

Takahiro Mishima, Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 31/20 (2006.01); H01L 31/0747 (2012.01); H01L 31/0224 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/202 (2013.01); H01L 31/022441 (2013.01); H01L 31/022491 (2013.01); H01L 31/0747 (2013.01); H01L 31/1804 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.


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