The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Jul. 02, 2014
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Tae-Kyung Oh, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H01L 29/66484 (2013.01); H01L 29/66666 (2013.01); H01L 29/7813 (2013.01);
Abstract

A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; and a low resistance layer contacting the high work function liner layer and the low work function liner layer, and partially filling the trench.


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