The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Oct. 19, 2015
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Yuji Asano, Atsugi, JP;

Junichi Koezuka, Atsugi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/477 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66969 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 21/477 (2013.01); H01L 27/1214 (2013.01); H01L 27/1225 (2013.01); H01L 27/1288 (2013.01); H01L 29/42384 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01);
Abstract

An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. The thin film transistor is formed in such a manner that a buffer layer including a high-resistance region and low-resistance regions is formed over an oxide semiconductor layer, and the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the low-resistance region of the buffer layer interposed therebetween.


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