The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Sep. 11, 2015
Applicant:

Magnachip Semiconductor, Ltd., Cheongju-si, KR;

Inventors:

Doo Yeol Ryu, Cheongju-si, KR;

Jeong Ho Cho, Hwaseong-si, KR;

Kyung Ho Lee, Cheongju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/28273 (2013.01); H01L 29/42324 (2013.01); H01L 29/7883 (2013.01);
Abstract

A non-volatile memory device includes a semiconductor substrate, a well region situated on the semiconductor substrate, a floating gate situated on the well region, a floating gate channel region, a control gate situated on both sides of the floating gate, a control gate channel region, and an ion implantation area for regulating a program threshold voltage integrally formed between an area underneath of the floating gate and the control gate and a foreside of the well region, wherein a doping concentration of the ion implantation area for regulating a program threshold voltage is greater than a doping concentration of the well region. Therefore, the non-volatile memory device of examples integrally forms an ion implantation area for regulating a program threshold voltage irrespective of a channel region of a floating gate and a control gate so as to guarantee durability of a non-volatile memory device.


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