The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Sep. 25, 2015
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Qiuhua Han, Shanghai, CN;

Jie Chen, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/49 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66636 (2013.01); H01L 21/265 (2013.01); H01L 29/4983 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66492 (2013.01); H01L 29/7834 (2013.01); H01L 29/7848 (2013.01); H01L 29/165 (2013.01);
Abstract

A method is provided for fabricating transistors. The method includes providing a semiconductor substrate. The substrate has a gate film and a mask film formed on a top surface. The mask film contains implanted carbon ions. The method further includes forming a mask layer by etching the mask film and then forming a gate layer by etching through the gate film using the mask layer as a mask until the substrate is exposed. The method also includes forming a first sidewall containing implanted carbon ions on the side surface of the gate layer and the mask layer; forming a stress layer in the substrate on both sides of the gate layer and the first sidewall; and forming a source region on one side of the gate layer and the first sidewall and a drain region on the other side of the gate layer and the first side wall.


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