The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Sep. 10, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Atsushi Oga, Yokkaichi, JP;

Mutsumi Okajima, Yokkaichi, JP;

Takeshi Yamaguchi, Yokkaichi, JP;

Hiroyuki Ode, Yokkaichi, JP;

Toshiharu Tanaka, Yokkaichi, JP;

Natsuki Fukuda, Yokkaichi, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/085 (2013.01); H01L 45/124 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/1675 (2013.01);
Abstract

According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.


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