The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Aug. 05, 2014
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Toru Hayashi, Kawasaki, JP;

Motoo Suwa, Kawasaki, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); G11C 11/4076 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 5/063 (2013.01); G11C 7/10 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/15311 (2013.01);
Abstract

An electronic device includes a mounting substrate, a first semiconductor component including a first semiconductor chip that operates in synchronization with a first clock signal and being mounted on a first semiconductor component mounting area of the mounting substrate, a second semiconductor component including a second semiconductor chip that operates in synchronization with a second clock signal and being mounted on a second semiconductor component mounting area of the mounting substrate, the second semiconductor component mounting area being next to the first semiconductor component mounting area, and a third semiconductor component including a third semiconductor chip that controls the first and second semiconductor chips and being mounted on a third semiconductor component mounting area of the mounting substrate, the third semiconductor component mounting area being next to the first and the second semiconductor component mounting areas.


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