The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Nov. 28, 2014
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Hongjun Xie, Beijing, CN;

Kun Cao, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G02F 1/1362 (2006.01); G09G 3/00 (2006.01); G09G 3/3266 (2016.01); G11C 19/00 (2006.01); G09G 3/20 (2006.01); G09G 3/32 (2016.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G02F 1/1362 (2013.01); G09G 3/006 (2013.01); G09G 3/20 (2013.01); G09G 3/32 (2013.01); G09G 3/3266 (2013.01); G09G 3/36 (2013.01); G11C 19/00 (2013.01); H01L 27/32 (2013.01); G09G 2310/021 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/08 (2013.01); G09G 2330/12 (2013.01);
Abstract

An array substrate, a display panel and a repairing method thereof are provided. In the array substrate, except the last gate line, both ends of each of the remaining gate lines are provided respectively with first leads connected to the gate line; in each group of gate integrated drive circuits, except a first level shift register, an input terminal of every other shift register is provided with a second lead connected to the input terminal; the first lead connected to one of the gate lines and the second lead connected to an input terminal of the shift register at the next level adjacent thereto have an overlapping area (A) therebetween, and are insulated from each other.


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