The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Nov. 04, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Robert W. Berry, Jr., Round Rock, TX (US);

Anand Haridass, Bangalore, IN;

Prasanna Jayaraman, Bangalore, IN;

Attorney:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 11/3409 (2013.01); G06F 11/349 (2013.01); G06F 9/30 (2013.01); G06F 11/3414 (2013.01); G06F 11/3466 (2013.01);
Abstract

A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.


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