The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2017
Filed:
Feb. 12, 2015
Applicant:
Tdk Corporation, Tokyo, JP;
Inventors:
Kenichi Takubo, Tokyo, JP;
Kazuaki Kishi, Tokyo, JP;
Assignee:
TDK Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/065 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2206/1014 (2013.01); G06F 2212/7211 (2013.01);
Abstract
The memory controller comprises a storage unit in which the Registered-System-Max-NOE is registered per logical area and a processor which registers, in the storage unit, the System-Max-NOE (the maximum value of multiple erasures respectively corresponded to multiple physical areas) at the time when allocating a spare physical area in one of the logical areas as the Registered-System-Max-NOE to be associated with the allocation destination logical area. The processor performs a wear leveling processing based on the Registered-System-Max-NOE per logical area.