The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Jan. 27, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Olivier Alavoine, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0868 (2016.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0646 (2013.01); G06F 3/0688 (2013.01); G06F 12/0215 (2013.01); G06F 12/0868 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/281 (2013.01); G06F 2212/305 (2013.01); G06F 2212/3042 (2013.01); G11C 7/1072 (2013.01);
Abstract

Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DRAM) for a predetermined number of future clock cycles. The DRAM is electrically coupled to a system on chip (SoC). Based on the future memory state data, one of a plurality of pending memory transactions is selected that speculatively optimizes DRAM efficiency. The selected memory transaction is sent to a shared cache controller. If the selected memory transaction results in a cache miss, the selected memory transaction is sent to a DRAM controller.


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