The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Mar. 23, 2015
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Xiangyan Zhang, Beijing, CN;

Yanbing Wu, Beijing, CN;

Wenbo Li, Beijing, CN;

Pan Li, Beijing, CN;

Qian Jia, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1335 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 21/84 (2006.01); H01L 21/82 (2006.01); H01L 23/50 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/133528 (2013.01); G02F 1/136227 (2013.01); H01L 21/768 (2013.01); H01L 21/82 (2013.01); H01L 21/84 (2013.01); H01L 23/481 (2013.01); H01L 23/50 (2013.01); H01L 27/124 (2013.01); H01L 27/1259 (2013.01); G02F 2001/13629 (2013.01); G02F 2001/133548 (2013.01); G02F 2001/136295 (2013.01); G02F 2201/123 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The embodiments of the present invention provide a substrate and a manufacturing method thereof, as well as a display device. The substrate comprises: a base substrate, a plurality of gate lines arranged in parallel, a first insulating layer that covers the gate lines, a plurality of data lines located on the first insulating layer and perpendicular to the gate lines, a second insulating layer that covers the data lines, and pixel electrodes of sub-pixel areas enclosed by the data lines and the gate lines; polarizing films that cover the pixel electrodes; and first auxiliary gate lines arranged on the second insulating layer and parallel to the gate lines, at least two portions on each of the first auxiliary gate lines being electrically connected with at least two corresponding portions on the gate line through via holes that penetrate the first insulating layer and the second insulating layer, the first auxiliary gate lines and the polarizing films are formed by performing a same patterning process to a same layer of transparent conductive material. The embodiments of the present invention can reduce signal delay in a display device, and can be used for manufacture of a display.


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