The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2017
Filed:
Dec. 22, 2015
Altera Corporation, San Jose, CA (US);
Joshua David Fender, East York, CA;
Benyamin Siman-Tov, Pleasanton, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Systems and methods for coalescing regions on a virtualized programmable logic device are provided. A first function is configured on a first subregion on the virtualized programmable logic device. The first subregion may border an unused subregion on the programmable logic device. The first function operated on the first subregion is migrated to a second function operated on a second subregion on the virtualized programmable logic device by mapping a first set of bits configuring the first subregion to a second set of bits configuring the second subregion for the second function. The first subregion is then released from the first function. The second function is configured to perform a same task with the first function, and the first subregion and the unused subregion together form a larger unused subregion on the virtualized programmable logic device. Similarly, multiple subregions can be migrated and vacated to form a larger available region.