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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9698309 B1

PDFFull Text
Date of Patent:
Jul. 04, 2017

Filed:

Jan. 06, 2016

Method for fabricating cmos compatible contact layers in semiconductor devices

Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Celso Cavaco, Leuven, BE;

Brice De Jaeger, Leuven, BE;

Marleen Van Hove, Blanden, BE;

Vasyl Motsnyi, Leuven, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:

McDonnell Boehnen Hulbert & Berghoff LLP

Primary Examiner:

Matthew Landau

Assistant Examiner:

Grant Withers

Int. Cl.
CPC ...
H01L 33/40 (2010.01); H01L 21/8252 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01); H01L 29/20 (2006.01); H01L 29/45 (2006.01); H01L 33/32 (2010.01); H01L 29/207 (2006.01);
U.S. Cl.
CPC ...
H01L 33/40 (2013.01); H01L 21/3245 (2013.01); H01L 21/32051 (2013.01); H01L 21/32134 (2013.01); H01L 21/8252 (2013.01); H01L 29/2003 (2013.01); H01L 29/452 (2013.01); H01L 33/325 (2013.01); H01L 29/207 (2013.01); H01L 33/32 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Find Patent Forward Citations

Cavaco, Celso. (2017). Method for fabricating cmos compatible contact layers in semiconductor devices (U.S. Patent No. 9698309). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9698309

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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