The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

May. 25, 2016
Applicant:

Enraytek Optoelectronics Co., Ltd., Shanghai, CN;

Inventors:

Huiwen Xu, Shanghai, CN;

Yu Zhang, Shanghai, CN;

Qiming Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/22 (2010.01); H01L 33/00 (2010.01); H01L 33/06 (2010.01); H01L 33/32 (2010.01); H01L 33/62 (2010.01); H01L 33/64 (2010.01); H01L 27/15 (2006.01);
U.S. Cl.
CPC ...
H01L 33/22 (2013.01); H01L 33/007 (2013.01); H01L 33/0095 (2013.01); H01L 33/06 (2013.01); H01L 33/32 (2013.01); H01L 33/62 (2013.01); H01L 33/647 (2013.01); H01L 27/153 (2013.01); H01L 33/0079 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0066 (2013.01); H01L 2933/0075 (2013.01);
Abstract

A high voltage LED flip chip includes two or more regions; a Mesa-platform, the Mesa-platform in each region has a first groove; a first electrode located on the Mesa-platform, an area between the first electrodes in two adjacent regions forms a second groove; a first insulation layer covering the Mesa-platforms and the first electrodes, the first insulation layer fills the second groove and partially fills the first groove, and a part of the first groove which is not filled forms a third groove; a fourth groove formed in the first insulation layer, the fourth groove exposes a surface of the first electrode; and an interconnection electrode, the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region. The LED formed has improved performance.


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