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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9698299 B1

PDFFull Text
Date of Patent:
Jul. 04, 2017

Filed:

Dec. 23, 2014

Integrated circuit combination of a target integrated circuit and a plurality of thin film photovoltaic cells connected thereto using a conductive path

Applicant:

Sol Chip Ltd., Haifa, IL;

Inventors:

Shani Keysar, Haifa, IL;

Reuven Holzer, Herzliya, IL;

Ofer Navon, Pardes Hanna, IL;

Ram Friedlander, Zichron Yaakov, IL;

Assignee:

Sol Chip Ltd., Haifa, IL;

Attorney:

M&B IP Analysts, LLC

Primary Examiner:

Duy T Nguyen

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 31/18 (2006.01); H01L 25/16 (2006.01); H01L 27/118 (2006.01); H01L 27/142 (2014.01); H01L 31/0392 (2006.01); H01L 31/046 (2014.01); H01L 25/00 (2006.01); H01L 31/0465 (2014.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 31/18 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 27/118 (2013.01); H01L 27/11898 (2013.01); H01L 27/142 (2013.01); H01L 31/0392 (2013.01); H01L 31/03921 (2013.01); H01L 31/03923 (2013.01); H01L 31/03925 (2013.01); H01L 31/046 (2014.12); H01L 31/0465 (2014.12); H01L 24/05 (2013.01); H01L 2224/05571 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13063 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); Y02E 10/50 (2013.01);
Abstract

A device having a plurality of thin film photovoltaic cells (PV) formed over a passivation layer. The device comprises a plurality of thin film photovoltaic (PV) cells formed over the passivation layer, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output. In an embodiment the passivation layer is formed over a target integrated circuit (TIC), the TIC having a top surface and a bottom surface.

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