The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2017
Filed:
Apr. 23, 2014
Applicant:
Sumitomo Electric Industries, Ltd., Osaka, JP;
Inventors:
Assignee:
Sumitomo Electric Industries, Ltd., Osaka-shi, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/105 (2006.01); H01L 31/0352 (2006.01); H01L 31/0304 (2006.01); H01L 31/18 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 31/035236 (2013.01); H01L 21/0243 (2013.01); H01L 21/0262 (2013.01); H01L 21/02389 (2013.01); H01L 21/02433 (2013.01); H01L 21/02458 (2013.01); H01L 21/02463 (2013.01); H01L 21/02466 (2013.01); H01L 21/02507 (2013.01); H01L 21/02543 (2013.01); H01L 21/02587 (2013.01); H01L 31/03046 (2013.01); H01L 31/105 (2013.01); H01L 31/1844 (2013.01); Y02E 10/544 (2013.01); Y02P 70/521 (2015.11);
Abstract
An epitaxial wafer of the present invention includes a substrate composed of a III-V compound semiconductor, a multiple quantum well structure composed of a III-V compound semiconductor and located on the substrate, and a top layer composed of a III-V compound semiconductor and located on the multiple quantum well structure. The substrate has a plane orientation of (100) and an off angle of −0.030° or more and +0.030° or less, and a surface of the top layer has a root-mean-square roughness of less than 10 nm.