Parallel bit line three-dimensional resistive random access memory

Abstract

Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.