The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Aug. 19, 2015
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Istvan Rodriguez, Chelsea, MA (US);

Christopher M. Laighton, Boxborough, MA (US);

Alan J. Bielunis, Hampstead, NH (US);

Assignee:

Raytheon Company, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 23/66 (2006.01); H01L 23/48 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 23/481 (2013.01); H01L 23/66 (2013.01); H01L 29/0696 (2013.01); H01L 29/41758 (2013.01); H01L 29/4238 (2013.01); H01L 2223/6622 (2013.01); H01L 2223/6627 (2013.01);
Abstract

A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.


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