The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Jul. 05, 2016
Applicants:

Bo-ra Lee, Incheon, KR;

Jae-ho Jeong, Suwon-si, KR;

Nam-gyu Baek, Suwon-si, KR;

Hyo-seok Woo, Hwaseong-si, KR;

Hyun-sook Yoon, Anyang-si, KR;

Kwang-yong Lee, Anyang-si, KR;

Inventors:

Bo-Ra Lee, Incheon, KR;

Jae-Ho Jeong, Suwon-si, KR;

Nam-Gyu Baek, Suwon-si, KR;

Hyo-Seok Woo, Hwaseong-si, KR;

Hyun-Sook Yoon, Anyang-si, KR;

Kwang-Yong Lee, Anyang-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 29/423 (2006.01); H01L 27/1157 (2017.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 23/562 (2013.01); H01L 27/1157 (2013.01); H01L 29/4238 (2013.01);
Abstract

A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.


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