The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Mar. 06, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Yusuke Umezawa, Kanagawa-ken, JP;

Shigeru Kinoshita, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 11/5628 (2013.01); G11C 16/3418 (2013.01); G11C 16/3436 (2013.01); G11C 16/30 (2013.01);
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes memory cell units, bit lines, word lines, and a controller. Each of the memory cell units includes a plurality of memory cells connected in series. Bit lines are connected respectively to the corresponding memory cell units. Each of the word lines is commonly connected to control gates of the corresponding memory cells of the memory cell units. The controller is configured to control a programming operation of data to the memory cells. The controller is configured to execute a first procedure including programming the data to the memory cell connected to the (4n−3)th (n being a natural number) bit line and the memory cell connected to the (4n−2)th bit line, and a second procedure including programming the data to the memory cell connected to the (4n−1)th bit line and the memory cell connected to the 4nth bit line.


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