The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2017
Filed:
Feb. 05, 2015
Applicant:
The Board of Trustees of the University of Illinois, Urbana, IL (US);
Inventors:
Assignee:
THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS, Urbana, IL (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 7/12 (2006.01); G11C 7/10 (2006.01); G11C 7/16 (2006.01); G11C 8/04 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/1006 (2013.01); G11C 7/16 (2013.01); G11C 8/04 (2013.01); G11C 8/08 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract
A compute memory system can include a memory array and a controller that generates N-ary weighted (e.g., binary weighted) access pulses for a set of word lines during a single read operation. This multi-row read generates a charge on a bit line representing a word stored in a column of the memory array. The compute memory system further includes an embedded analog signal processor stage through which voltages from bit lines can be processed in the analog domain. Data is written into the memory array in a manner that stores words in columns instead of the traditional row configuration.