The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Apr. 14, 2014
Applicant:

Shanghai Jiao Tong University, Shanghai, CN;

Inventors:

Haibing Guan, Shanghai, CN;

Jian Li, Shanghai, CN;

Ruhui Ma, Shanghai, CN;

Minjun Zhu, Shanghai, CN;

Fanfu Zhou, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/24 (2006.01); G06F 15/173 (2006.01); G06F 9/48 (2006.01); G06F 9/455 (2006.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4812 (2013.01); G06F 9/45504 (2013.01); G06F 9/45558 (2013.01); G06F 9/461 (2013.01); G06F 9/48 (2013.01); G06F 13/24 (2013.01); G06F 2009/45579 (2013.01);
Abstract

The invention discloses a method for dynamic interrupt balanced mapping method based on the current scheduling states of VCPUs. When the virtual I/O APIC of an SMP virtual machine needs to map a virtual interrupt into a VCPU of the virtual machine after receiving the virtual interrupt, a part of VCPUs in the active state are analyzed according to the scheduling states of all VCPUs of the current VM in a VMM scheduler, and the virtual interrupt is mapped into the active VCPUs to obtain lower interrupt processing delay. If a plurality of VCPUs are in the active state simultaneously, the interrupt load of each active VCPU is considered further, and the interrupt is mapped into the active VCPU with the current lowest current load to further ensure balancing of interrupt processing loads of all VCPUs, and therefore, the loads of VCPUs in the SPMP structure are more symmetrical to promote balancing of the overall performance of all VCPUs in the SMP structure.


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