The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Dec. 24, 2013
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Naoya Okada, Tokyo, JP;

Yusuke Nonaka, Tokyo, JP;

Akihiko Araki, Tokyo, JP;

Shintaro Kudo, Tokyo, JP;

Makio Mizuno, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 3/06 (2006.01); G06F 12/0875 (2016.01); G06F 12/06 (2006.01); G06F 12/0868 (2016.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 3/0689 (2013.01); G06F 12/0638 (2013.01); G06F 12/08 (2013.01); G06F 12/0868 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01); G06F 2212/222 (2013.01); G06F 2212/2228 (2013.01);
Abstract

A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.


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