The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

May. 13, 2016
Applicant:

Oracle International Corporation, Redwood Shores, CA (US);

Inventors:

Leick D. Robinson, Austin, TX (US);

Avadh Pratham Patel, Cedar Park, CA (US);

Ashok V. Krishnamoorthy, San Diego, CA (US);

Alan P. Wood, San Jose, CA (US);

Assignee:

ORACLE INTERNATIONAL CORPORATION, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J 14/02 (2006.01); H04Q 11/00 (2006.01); G02B 6/35 (2006.01); H04B 10/40 (2013.01); H04B 10/25 (2013.01);
U.S. Cl.
CPC ...
H04Q 11/0062 (2013.01); G02B 6/3542 (2013.01); G02B 6/3596 (2013.01); H04B 10/2504 (2013.01); H04B 10/40 (2013.01); H04J 14/02 (2013.01); H04J 14/0212 (2013.01); H04Q 11/0005 (2013.01); H04Q 2011/009 (2013.01);
Abstract

A macro-switch is described. This macro-switch includes facing integrated circuits, one of which implements optical waveguides that convey optical signals, and the other which implements control logic, electrical switches and memory buffers at each of multiple switch sites. Moreover, the macro-switch has a fully connected topology between the switch sites. Furthermore, the memory buffers at each switch site provide packet buffering and congestion relief without causing undue scheduling/routing complexity. Consequently, the macro-switch can be scaled to an arbitrarily large switching matrix (i.e., an arbitrary number of switch sites and/or switching stages).


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