The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Aug. 31, 2016
Applicant:

Square, Inc., San Francisco, CA (US);

Inventors:

Afshin Rezayee, Richmond Hill, CA;

Ravi Shivnaraine, Brampton, CA;

Alain Rousson, Toronto, CA;

Yue Yang, Thornhill, CA;

Kajornsak Julavittayanukool, Toronto, CA;

Assignee:

Square, Inc., San Francisco, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 5/156 (2006.01); H03K 19/20 (2006.01); H03K 19/173 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/003 (2013.01); H03K 5/1565 (2013.01); H03K 19/1737 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01);
Abstract

A transition glitch suppression circuit can be used to remove unwanted glitches occurring within a time delay of the rising edge or falling edge of a signal. The transition glitch suppression circuit has a delay element that can delay the input signal by the time delay to generate a delayed input signal. The transition glitch suppression circuit also has first and second logic circuits that process the input signal and the delayed input signal to generate corresponding outputs. A multiplexer provides the output signal for the suppression circuit by selecting between the output of the first logic circuit and the output of the second logic circuit based on the value of the output signal.


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