The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

May. 13, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xinxin Yu, Santa Clara, CA (US);

Ashok Swaminathan, Cardiff, CA (US);

Christian Venerus, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/03 (2006.01); H03K 3/011 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0315 (2013.01); H03K 3/011 (2013.01); H03L 7/0995 (2013.01); H03L 7/0997 (2013.01);
Abstract

A method and apparatus for controlling a supply sensitivity of a ring oscillator stage are provided. The apparatus is configured to generate, via a voltage biasing module, a first bias signal for a PMOS biasing module based on a supply voltage and a second bias signal for a NMOS biasing module based on the supply voltage, bias, via the PMOS biasing module, triode PMOS degeneration of the inverting module based on the first bias signal, bias, via the NMOS biasing module, triode NMOS degeneration of the inverting module based on the second bias signal, receive an input via an inverting module, and output, via the inverting module, an inverted version of the received input based on the biased triode NMOS degeneration and the biased triode PMOS degeneration.


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