The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Apr. 09, 2015
Applicant:

Alphabet Energy, Inc., Hayward, CA (US);

Inventors:

Jeffrey M. Weisse, Sunnyvale, CA (US);

John P. Reifenberg, Pleasanton, CA (US);

Lindsay M. Miller, Berkeley, CA (US);

Matthew L. Scullin, San Francisco, CA (US);

Assignee:

Alphabet Energy, Inc., Hayward, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 35/34 (2006.01); H01L 35/28 (2006.01); H01L 35/30 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/326 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0676 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/306 (2013.01); H01L 21/30604 (2013.01); H01L 21/326 (2013.01); H01L 29/16 (2013.01);
Abstract

Under one aspect, a plurality of silicon nanostructures is provided. Each of the silicon nanostructures includes a length and a cross-section, the cross-section being substantially constant along the length, the length being at least 100 microns. Under another aspect, a method of making nanostructures is provided that includes providing a silicon wafer including a thickness and first and second surfaces separated from one another by the thickness; forming a patterned layer of metal on the first surface of the silicon wafer; generating a current through the thickness of the silicon wafer, the metal oxidizing the silicon wafer in a region beneath the patterned layer of the metal; and exposing the silicon wafer to an etchant in the presence of the current, the etchant removing the oxidized region of the silicon wafer so as to define a plurality of nanostructures. Methods of transferring nanowires also are provided.


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