The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Sep. 01, 2015
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Dong Yean Oh, Gyeonggi-do, KR;

Nam Kyun Park, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2454 (2013.01); H01L 29/0847 (2013.01); H01L 29/42376 (2013.01); H01L 29/7827 (2013.01); H01L 29/7831 (2013.01); H01L 45/06 (2013.01); H01L 45/126 (2013.01); H01L 45/1233 (2013.01);
Abstract

A vertical transistor may include a pillar, a gate and an electric field-buffering region. The pillar may be vertically extended from a surface of a semiconductor substrate. The pillar may include a source, a channel region and a drain. The gate may be formed on an outer surface of the pillar. The gate may be overlapped with the channel region, a portion of the source configured to make contact with the channel region, and a portion of the drain configured to make contact with the channel region. The electric field-buffering region may be formed in the portion of the drain overlapped with the gate. The electric field-buffering region may have a band gap different from a band gap of a material in the pillar.


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