The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Mar. 03, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Kil-Soo Kim, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/481 (2013.01); H01L 23/49838 (2013.01); H01L 23/50 (2013.01); H01L 24/49 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/157 (2013.01); H01L 2924/1579 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/15788 (2013.01);
Abstract

Provided is a semiconductor device having as many input/output pads as possible using a chip having a small number of input/output pads. The semiconductor device includes a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively; wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.


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